Kaleem Ullah: CSSP University of Punjab Lahore Pakistan, firstname.lastname@example.org
Saira Riaz: CSSP University of Punjab Lahore Pakistan, email@example.com
M. Habib: CSSP University of Punjab Lahore Pakistan, firstname.lastname@example.org
F. Abbas: CSSP University of Punjab Lahore Pakistan, email@example.com
S. Naseem: CSSP University of Punjab Lahore Pakistan, firstname.lastname@example.org
G. Abbas: Bahauddin Zakarya University Multan Pakistan, email@example.com
K. Ullah, S. Riaz, M.Habib, F. Abbas, S. Naseem, G. Abbas "Effect of High Temperature on the Impact Ionization of N-Channel Fully Depleted SOI MOSFET" International Journal of Engineering Works, Vol. 1, Issue 3, PP. 48-51, Dec. 2014.
 J.T. Lin, Y.C. Eng, T.Y. Lee and K.C. Lin, “Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI” 20th International Conference on VLSI Design,2007.
 Ohata , M. Casse and O. Faynot, “Electrical characteristics related to silicon film thickness in advanced FD SOI–MOSFETs”, Solid-State Electronics 52 (2008),pp. 126–133.
 R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, M. Steadele, W. Reosner, “Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime”, Solid-State Electronics 47 (2003) pp.1199–1203
 Deok-Su Jeon and Dorothea E. Burk, “A Temperature-Dependent SO1 MOSFET Model for High-Temperature Application (270C -3000C), IEEE Transactions on electron devices,38(1991), pp.2101-2111.
 A.K. Goel and T.H. Tan, High-temperature and self-heating effects in fully depleted SOI MOSFETs, Microelectronics Journal 37 (2006),pp. 963–975..
 M. J Gilbert, D. K. Ferry, “Discrete dopant effect in ultra small fully depleted ballistic SOI MOSFET”, Superlattices and Microstructures 34 (2003) pp.277-282.
 B. Jharia, S.Sarkar, R.P.Agarwal, “Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET”, Proceedings of the Sixth International Symposium on Quality Electronic Design 2005.
 N.Goel and A. Tripathi , “Temperature effects on Threshold Voltage and Mobility for Partially Depleted SOI MOSFET”, International Journal of Computer Applications 42 (2012), pp.56-58.
 S.J Kim, T.H Shim and J.G. Park, “Electrical behavior of ultra-thin body silicon-on-insulator n-MOSFETs at a high operating temperature”, Journal of Ceramic Processing Research,10 (2009), pp.507-511
 . K.Rajendran and G.S.Samudra, “Modelling of transconductance-to-current ratio (gm/ID) analysis on double-gate SOI MOSFETs”, Semicond. Sci. Technol. 15 (2000),pp.139–144.
 J. B. Kuo, S. H. Lin, Low voltage SOI CMOS VLSI Device and circuites, Wiley 2001.