Temperature and Channel width Dependence of Novel Lateral Gate VJFET

2D numerical simulation of normally off vertical N-channel JFET with novel internal lateral gate configuration designed on a 9.4 ?m, 7 × 1015 cm?3 doped drift layer is presented. The study covers an interval of blocking voltages ranging from 600 V to 933 V for various temperatures and channel widths. The effect of elimination of vertical JFET gates and variation in channel width on the on-state/breakdown performance is carefully investigated. The device performance has been compared in terms of blocking voltages, specific on-state resistance and maximum output current density in the temperature range from room temperature up to 473 K. Normally-off operation with blocking voltage (Vbl) of 933 V is demonstrated for a gate voltage of -20 V. The goal of this work is to predict the performance of lateral gate VJFET configuration and have a deep insight into the relationship between the device’s electrical/thermal characteristics and channel thickness. The detailed investigation reveals that lateral gate configuration offers less resistance to leakage current reducing the blocking capability of the device. Though, it’s excellent on state performance in terms of high saturation current (1.23A) and low on-resistance (3.6 m ?) makes this VJFET an excellent device for fast power switching applications.

Muhammad Farooq Saleem1,2, Muhammad Khalid1,3, Yasir Abdul Haleem1,2, Hafiz Tariq Masood1,2, Rashid Khan2,4, Mehdi Khan2, Ghulam Abbas Ashraf5,6, Awais Siddique Saleemi7,8, Saira Riaz1, Shahzad Naseem1

First Author: Centre of Excellence in Solid State Physics ,University of the Punjab, Lahore, Pakistan, Farooq_chishty@yahoo.com
Second Author: University of Science and Technology of China, Hefei, Anhui, China, Farooq@mail.ustc.edu.cn
Third Author: Department of Physics, NED University of Engineering and Technology, Karachi, Pakistan
Fourth Author: Department of Physics, Quaid-i-Azam University, Islamabad, Pakistan
Fifth Author: Department of Physics , Allama Iqbal Open University, Islamabad, Pakistan
Sixth Author: Department of Physics and Astronomy, Shanghai Jiao Tong University, Shanghai, China
Seventh Author: Department of Physics, COMSATS Institute of Information Technology, Islamabad, Pakistan
Eigth Author: Tsinghua University, Beijing, China

Muhammad Farooq Saleem, Muhammad Khalid, Yasir Abdul Haleem, Hafiz Tariq Masood, Rashid Khan, Mehdi Khan, Ghulam Abbas Ashraf, Awais Siddique Saleemi, Saira Riaz, Shahzad Naseem,"Temperature and Channel width Dependence of Novel Lateral Gate VJFET" International Journal of Engineering Works, Vol. 3, Issue 1, PP. 1-5, February 2016. 

[1] Q. Zhang, and A. K. Agarwal, “Design and technology considerations for SiC bipolar devices: BJTs, IGBTs, and GTOs ” J. Phys. Stat. Sol A., vol. 206 pp. 2431-2456 2009
[2] R. Perez, D. Tournier, A. P Tomas, P. Godignon, N. Mestres, and J. Millan, “Planar Edge Termination Design and Technology Considerations for 1.7-kV 4H-SiC PiN Diodes,” IEEE Trans. Elect. Dev., vol. 52 pp. 2309-2316 2005
[3] M. Ghezzo, D. M. Brown, E. Downey, J. Kretchmer, W. Hennessy, D. L. Polla, and H. Bakhru, “Nitrogen-Implanted SiC Diodes Using High-Temperature Implantation” IEEE Elect. Dev. Lett., vol. 13 pp. 639-641 1992
[4] S. Nakamura, Y. Harada, and M. Seno, “Novel metalorganic chemical vapor deposition system for GaN growth,” J. Appl. Phys. Lett., vol. 58 pp. 2021-2023 1991
[5] V.V. Zhirnov, G. J. Wojak, W.B. Choi, J. J. Cuomo, and J. J. Hren, “Wide band gap materials for field emission devices,” J. Vac. Sci. Technol., vol. 15 pp. 1733-1738 1997
[6] Ed. G. L. Harris, EMIS Data Reviews Series, No 13, Short Run Press., Exeter, England, 1995
[7] T. P. Chow, N. Ramungul, and M. Ghezzo, “Semiconductor Power Devices, Power Semiconductor Materials and Devices, ” Mat. Res. Soc. Proc., vol. 483 pp. 89 1998
[8] E. G. Acheson, “production of artificial crystalline carbonaceous materials, carborundum ,” English Patent., pp. 17911 (1892)
[9] J. L. Hudgins, G. Simin, E. Santi, and M. A. Khan, “An assessment of wide bandgap semiconductors for power devices, ” IEEE Trans. Pow. Elec., vol. 18 pp. 907-914 2003
[10] T. Nakamura, M. Miura, N. Kawamoto, Y. Nakano, T. Otsuka, K. Oku-Mra, and A. Kamisawa, “Development of SiC diodes, power MOSFETs and intelligent power modules” Physica Status Solidi (a)., vol. 206 pp. 2403-2416 2009
[11] R. K. Malhan, M. Bakowski, Y. Takeuchi, N. Sugiyama, A. Schöner, “Design, process, and performance of all-epitaxial normally-off SiC JFETs,” Phys. Stat. Sol. (a)., vol. 206 pp. 2308-2328 2009
[12] S. H. Ryu, S. Krishnaswami, B. Hull, J. Richmond, A. Agarwal, and A. Hefner,“10 kV, 5 A, 4H-SiC power DMOSFET,” Proc. ISPSD., pp. 4-8 2006
[13] R. S. Howell, S. Buchoff, S. V. Campen, T. R. McNutt, A. Ezis, B. Nechay, C. F. Kirby, M. E. Sherwin, R. C. Clarke, and R. Singh, ““A 10 kV large-area 4H-SiC power DMOSFET with stable subthreshold behavior independent of temperature,”” IEEE Trans. Elec. Dev., vol. 55 pp. 1807-1815 2008
[14] S. H. Ryu, S. Das, S. Haney, A. Agarwal, A. Lelis, B. Geil, and C. Scozzie, “Critical issues for MOS based power devices in 4H-SiC,” Mater. Sci. Forum., vol. 615 pp. 743-748 2009
[15] J. H. Zhao, K. Tone, X. Li, P. Alexandrov, L. Fursin, and M. Weiner, “3.6 m?cm2, 1726V 4H-Sic Normally-off Trenched and-Implanted Vertical JFETs,” Proc. ISPSD., pp. 50-53 2003
[16] V. Veliadis, E. J. Stewart, H. Hearne, M. Snook, A. Lelis, and C. Scozzie, “A 9-kV Normally-ON Vertical-Channel SiC JFET for Unipolar Operation” IEEE Elec. Dev. Lett., vol. 31 pp. 470-472 2010
[17] M. B. Berkani, D. Othman, S. Lefebvre, S. Moumen, Z. Khatir, and T. B. Sallah, “Ageing of SiC JFET transistors under repetitive current limitation conditions,” Microelec. Rel., vol. 50 pp. 1532-1537 2010
[18] G. Kelner, M. S. Shur, S. Binari, K. J. Sleger, and H. Kong, “High-Transconductance ?-Sic Buried-Gate JFET’s,” IEEE Trans. Elec. Dev., vol. 36 pp. 1045-1049 1989
[19] M. Bakowski, “Prospects and Development of Vertical Normally-off JFETs in SiC” Jr. Telecom. and IT., vol. 4 pp. 25-36 2009
[20] Sentaurus TCAD Copyright © 2009 Synopsys, Inc.
[21] J. H. Zhao, K. Tone, X. Li, P. Alexandrov, L. Fursin, and M. Weiner, “3.6 m? cm2, 1726 V 4H-SiC normally-off trenched and-implanted vertical JFETs and circuit applications,” IEEE Proc.-Circuits Devices Syst., vol. 3 pp. 231-237 2004
[22] “TCAD Simulation of Silicon Carbide Devices: Part I. Models and Parameters,” TCAD News., vol. 3 2006
[23] M. L. Heldwein, and J. W. Kolar, , “A novel SiC J-FET gate drive circuit for sparse matrix converter applications,” Proc. Nineteenth Ann. IEEE Appl. Pow. Elec. Conf. Expos., Anaheim, USA., pp. 1 116-121 2004
[24] J. K. Lim, G. Tolstoy, D. Peftitsis, J. Rabkowski, M. Bakowski, H. P. Nee, “Comparison of Total Losses of 1.2 kV SiC JFET and BJT in DC-DC Converter Including Gate Driver” Mater. Sci. Forum., vol. 679-680 pp. 649-652 2010
[25] V. Veliadis, T. McNutt, M. Snook, H. Hearne, P. Potyraj, J. Junghans, and C. Scozzie, “Large Area Silicon Carbide Vertical JFETs for 1200?V Cascode Switch Operation,” Int. J. Power manag. Electr., vol. 29 pp. 1-8 2008